1. Field of the Invention
The present invention relates to a bootstrap circuit particularly suitable for a low voltage driven bootstrap circuit to be used with a voltage booster for a semiconductor memory such as DRAM and a flash memory.
2. Description of the Related Art
A charge pump circuit is used as a voltage booster for a semiconductor memory such as DRAM and a flash memory. The voltage booster is required to generate a desired high and stable potential in a predetermined time. In order to boost a voltage at high speed, a charge pump circuit has been used to which an input clock having a voltage higher than a power source voltage V.sub.DD is supplied.
A conventional bootstrap circuit has a structure such as shown in FIG. 1. The operation of this bootstrap circuit will be described with reference to FIGS. 2A to 2D. FIGS. 2A to 2D show waveforms of potentials changing with time at an input terminal IN, a node N.sub.121, a node N.sub.122, and a node N.sub.123 (output terminal OUT), respectively of the circuit shown in FIG. 1.
As the potential at the input terminal IN rises as shown in FIG. 2A from the ground potential V.sub.SS to the power source voltage V.sub.DD during the time period from time t.sub.1 to time t.sub.2, the potential at the node N.sub.123 connected via an N-channel enhancement MOS transistor M.sub.121 to the input terminal IN starts rising from the ground potential V.sub.SS as shown in FIG. 2D. The transistor M.sub.121 is in an on-state with the power source voltage V.sub.DD being applied to its gate. On the other hand, the potential at the node N.sub.122 connected via an inverter IV.sub.121 to the input terminal IN starts gradually lowering from the power source voltage V.sub.DD toward the ground potential V.sub.SS by the function of a capacitor C.sub.122 as shown in FIG. 2C. At this time, however, the potential at the node N.sub.121 remains to be the ground potential V.sub.SS as shown in FIG. 2B because an N-channel enhancement MOS transistor M.sub.123 with its gate being connected to the node N.sub.122 is in an on-state.
After the potential at the node N.sub.122 continues lowering and becomes lower than the threshold voltage of the transistor M.sub.123, the transistor M.sub.123 changes from the on-state to the off-state. On the other hand, after the potential at the node N.sub.123 continues rising and becomes higher than the threshold voltage of an N-channel enhancement transistor M.sub.122 with its gate connected to the node N.sub.123, the transistor M.sub.122 changes from the off-state to the on-state. As a result, the potential at the node N.sub.121 starts rising from the ground potential V.sub.SS to the power source voltage V.sub.DD (at time t.sub.3 shown in FIGS. 2B).
As the potential at the node N.sub.121 starts rising, the potential at the node N.sub.123 further rises by the amount corresponding to a rise of the potential at the node N.sub.121 because of the function of the capacitor C.sub.121. With the feedback function of the capacitor C.sub.121, the potential at the node N.sub.123 (i.e., output terminal OUT) rises higher than the power source voltage V.sub.DD (at time t.sub.4 shown in FIG. 2D). At the time when the potential at the node N.sub.123 becomes the power source voltage V.sub.DD, a potential difference between the gate and source/drain of the transistor M.sub.121 is small. Therefore, regardless of the higher potential at the node N.sub.123 than the power source voltage V.sub.DD, current will not flow from the node N.sub.123 to the input terminal IN.
Next, as the potential at the input terminal IN lowers as shown in FIG. 2A from V.sub.DD to V.sub.SS during the time period from time t.sub.5 to time t.sub.7, the potential at the node N.sub.122 connected via the inverter IV.sub.121 to the input terminal IN starts rising as shown in FIG. 2C. When the potential at the node N.sub.122 exceeds the threshold voltage of the transistor M.sub.123 (at time t.sub.6), the transistor M.sub.123 changes from the off-state to the on-state and the potential at the node N.sub.121 starts lowering as shown in FIG. 2B. As a result, the potential at the node N.sub.123 also starts lowering as shown in FIG. 2D. When the potential at the node N.sub.123 becomes lower than the threshold voltage of the transistor M.sub.123, the transistor M.sub.122 changes from the on-state to the off-state and the node N.sub.121 is disconnected from the power source terminal. On the other hand, as the potential at the input terminal IN lowers and the potential at the node N.sub.123 lowers, the transistor M.sub.121 with its gate to which the power source voltage V.sub.DD is applied changes from the on-state to the off-state, and current flows from the node N.sub.123 to the input terminal IN so that the potential at the node N.sub.123 becomes the ground potential V.sub.SS (at time t.sub.8 show in FIG. 2D). Then, at time t.sub.9 the potentials at both the nodes N.sub.121 and N.sub.122 become the ground potential V.sub.SS (refer to FIGS. 2B and 2C).
With the above operations, a pulse signal having a larger voltage than the power source voltage V.sub.DD is obtained at the output terminal OUT, and the pulse signal can be used as a clock input to a charge pump circuit.
Although the conventional bootstrap circuit described above can obtain a pulse signal having a higher voltage than the power source voltage V.sub.DD, the boost of the output voltage is not still sufficient. Specifically, as the potential at the node N.sub.121 of the circuit shown in FIG. 1 rises to the power source voltage V.sub.DD, the output voltage should rise to 2 V.sub.DD in an ideal case. However, in an actual case, it rises only to 2 V.sub.DD -V.sub.th because of the threshold voltage V.sub.th of the transistor M.sub.121 which functions as a switching transistor (refer to FIG. 2D).
Further, in the conventional bootstrap circuit, it is relatively difficult for the transistor M.sub.122 to turn on because it is an N-channel transistor. The conventional bootstrap circuit is therefore associated with a problem that linearity of the rise of the output pulse is insufficient. If the bootstrap circuit is driven at a low power source voltage, particularly at about 1 V, the transistor M.sub.122 does not turn on in some cases.
Still further, in the conventional bootstrap circuit, the voltage fall at the node N.sub.123 upon the fall of the output pulse is achieved by flowing current via the transistor M.sub.121 to the input terminal IN. A voltage fall at the node N.sub.123 is therefore relatively slow. This results in a problem of a long fall time of the output pulse.